The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 1997

Filed:

Aug. 27, 1996
Applicant:
Inventors:

Rodney Gamache, Merrimac, NH (US);

Stuart Farnham, Brookline, NH (US);

Michael Harvey, Nashua, NH (US);

William A Laing, Newbury, GB;

Kathleen Morse, Hollis, NH (US);

Michael Uhler, Marlboro, MA (US);

Assignee:

Digital Equipment Corporation, Maynard, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395800 ; 395674 ; 395287 ; 395728 ; 364D / ; 364D / ;
Abstract

A plurality of processors each includes a central processor unit for processing programs at predetermined synchronization priority levels and a cache memory. A memory shared by all of the processors includes an synchronization level table which identifies a processor operating at each synchronization priority level. A common bus interconnects the processors and the memory. When a processor is to execute a program, it adjusts its synchronization priority level to a predetermined synchronization priority level by accessing the synchronization level table over the common bus to determine whether the level is accessible and, if so, places an entry in the table to indicate that the synchronization priority level is occupied. If the synchronization priority level is not accessible, the processor continually monitors the entry in the table over the common bus to determine when it is accessible by monitoring its cache, which contains a copy of the table entry associated with the synchronization priority level. When the synchronization priority level becomes accessible, the cache copy is invalidated so that the processor then has to use the table.


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