The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 1997
Filed:
Mar. 17, 1995
Applicant:
Inventors:
Sandip Kundu, Austin, TX (US);
Andreas Kuehlmann, Poughkeepsie, NY (US);
Arvind Srinivasan, Sunnyvale, CA (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364488 ;
Abstract
A technique for extracting a gate level logic model from transistor networks has been described. The resultant logic model can be technology dependent or technology independent, depending on control parameters and environment of the program. It handles all CMOS logic families including static, precharge, pass CMOS switching network and self-resetting families. The output gate level model can be used in variety of applications including but not limited to logic simulation, verification, test generation, debug, diagnosis, etc.