The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 1997

Filed:

Dec. 09, 1994
Applicant:
Inventor:

Yoshikazu Kurisu, Ichikawa, JP;

Assignee:

Uniden Corporation, Chiba, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B / ;
U.S. Cl.
CPC ...
455126 ; 455115 ; 375216 ; 375284 ;
Abstract

In a DC offset circuit for a Cartesian loop, a DSP supplies step by step a slope voltage from a minimum DC output voltage, up to a maximum DC output voltage, to input sections of operational amplifiers for modulation. This arises each time transmission is started in a state where a signal Q' and a signal I', each based on only a carrier wave, are outputted from a quadrature demodulator. When comparators detect that output from operational amplifiers is 0 V, the DSP decides a value of the slope voltage then as a DC offset voltage value. Operation is started centering on this DC offset voltage value.


Find Patent Forward Citations

Kurisu, Yoshikazu. (1997). Dc offset circuit for cartesian loop (U.S. Patent No. 5628059). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5628059

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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