System and method for controlling a peripheral bus clock signal during a

Abstract

A system and method for controlling a peripheral bus clock signal through a slave device are provided that accommodate a power conservation scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. Upon system reset, the BIOS boot code reads a configuration register MAXLAT within each alternate bus master. The contents of the configuration register are indicative of how often the particular master may require access to the peripheral bus. Upon reading the MAXLAT field of each master, the system sets a timer in accordance with the MAXLAT value corresponding to the master which requires the most frequent access to the peripheral bus. If the master requiring the peripheral bus most frequently specifies a maximum latency time of, for example, 2 microseconds, the system sets the timer to cycle (or trigger) every one microsecond (i.e., one-half of the specified maximum latency time). Thereafter, if a decision is made by the power management unit to stop the peripheral bus clock, the timer begins cycling. Upon lapse of each microsecond, the timer causes the clock generator to provide at least one clock edge (i.e., a clock one-shot or multi-shot). This ensures that any bus master coupled to the peripheral bus can generate a synchronous bus request signal to obtain mastership of the peripheral bus even though that master is incapable of generating a clock request signal.