Address transition detection circuit for a memory device having signal

Abstract

An address transition detection circuit for a memory device, by which an address transition detect signal having a pulse width required for operating the memory device is outputted regardless of a pulse width of an address signal inputted to the memory device to thereby prevent any malfunction of the memory device, includes a NOR gate for NORing the inputted address signal and a chip select signal; a latch for latching an output signal of the NOR gate by first to third input delay signals to output first and second latch signals; first and second signal delays for respectively delaying the first and second latch signals provided from the latch for a predetermined time to respectively output first and second delay signals; and a signal output unit for outputting the address transition detect signal in accordance with the first and second latch signals respectively provided from the latch and the first and second delay signals respectively provided from the first and second signal delays.