The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 1997

Filed:

Feb. 23, 1996
Applicant:
Inventors:

Kazuyuki Yamasaki, Tokyo, JP;

Teiichiro Nishizaka, Tokyo, JP;

Kazutaka Otsuki, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365104 ; 36518516 ; 36518517 ; 36518513 ;
Abstract

In a semiconductor memory comprising one main bit line D1, a pair of main ground lines VG1 and VD2, a plurality of memory cell banks to be selectively connected to the main bit line D1 and the main ground lines VG1 and VD2, and a plurality of word lines W1 to Wn extending through the memory cell banks, each of the memory cell banks includes a plurality of wirings L1, L2, L3, L4 and L5 located in parallel to each other, and a threshold of a block selection transistor BT11 connected between the main bit line D1 and the wiring L3, is lower than that of block selection transistors BT12 and BT13 connected between the main bit line D1 and the wiring L2 and between the main bit line D1 and the wiring L4, respectively.


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