Bit line structure with bit line pass over configuration

Abstract

A bit line structure is disclosed. Which includes: sense amplifiers each connected to two pairs of bit lines BL and /BL through bit line selecting switches, to the bit line a plurality of cells are connected, includes: a first bit line pair BL and /BL and a second bit line pair BL and /BL formed by dividing a bit line disposed within a same column respectively in a cell array; a first connecting bit line for connecting the bit line BL of said second bit line pair to said sense amplifier; a second connecting bit line for connecting the bit line /BL of said second bit line pair to said sense amplifier; said second connecting bit line having two crossing sections 25 crossing with another second connecting bit line for connecting a bit line BL of a second bit line belonging to an adjacent sense amplifier; and bit line selecting switches for connecting said first bit line pair and said second bit line pair respectively to said sense amplifier, whereby a number of memory cells connected to each bit line is reduced to 1/2 compared with the conventional technique, the bit lines are arranged 3-dimensionally to eliminate the area loss in carrying out the layout, and particularly, the connecting bit lines are made of a conductive material which has a smaller resistance than a conductive material of the bit lines.