Non-volatile multi-state memory device with memory cell capable of

Abstract

A data register for holding input digital data, a resistance dividing circuit for generating a plurality of analog voltages, a decoder for decoding the data of the data register and selectively outputting one of a plurality of analog voltages and a comparator for comparing this decoded output with an analog amount read from a memory cell are provided. In write mode, this memory device sets data to be written in the data register and writes an analog amount corresponding to the set data in the memory cell, in read mode, the apparatus sequentially sets in the data register digital data updated in sequence from a designated value, executes comparison at the comparator for each setting and terminates the digital data setting in response to the comparison result at the data register, thus digital data corresponding to the analog amount read from the memory cell is thereby obtained at the data register. As a result, circuit configuration can be simplified and circuit scale reduced.