The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 1997

Filed:

Aug. 08, 1994
Applicant:
Inventor:

Geert Deveirman, Tustin, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H04B / ;
U.S. Cl.
CPC ...
327353 ; 327552 ; 327560 ; 330109 ; 330304 ; 330305 ; 330254 ;
Abstract

A high-frequency integrated continuous-time filter with built-in test mode. The present invention provides the ability to easily track the cutoff frequency of the filter without the additional power and area requirements and noise sources present in prior art master/slave tuning schemes. Furthermore, the filter being tested is the actual filter that is used to process signals, unlike the prior art where a similar but separate filter or oscillator is used to tune the bias values for both circuits. Better tuning accuracy is thus obtained in the present invention. The circuit is designed to oscillate in test mode at the cutoff frequency of the filter. Oscillation is achieved by moving the poles of the filter from the left half-plane either onto the imaginary axis or into the right half-plane. The filter frequency accuracy is established by trimming the frequency of the oscillation in test mode during wafer probe or by adjusting the circuit biasing to tune the cutoff frequency in test mode during power-up or between reads in a memory system. The oscillation is disabled during normal operation of the filter.


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