The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 1997
Filed:
Aug. 30, 1995
Matthew H Childs, Arlington, TX (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A controller for initiating an insertion of one or more wait states on a signal bus includes registers, AND logic circuits, a counter and a OR logic circuit. One register is for connecting to a signal bus and receiving therefrom a clock signal and in response thereto receiving and latching an address strobe signal to provide a latched address strobe signal. One AND logic circuit is for receiving the latched address strobe signal, connecting to the signal bus and receiving therefrom an address write signal and a chip select signal and logically. ANDing the latched address strobe signal, the address write signal and the chip select signal to provide a first ANDed signal. Another register is for receiving a second clock signal and in response thereto receiving and latching the first ANDed signal to provide a first latched ANDed signal. Another AND logic circuit is for receiving and logically ANDing the first latched ANDed signal and a decoded address signal to provide a second ANDed signal. The counter is for receiving the second ANDed signal and the second lock signal and in response thereto providing a multiple-bit count signal. The OR logic circuit is for receiving and logically ORing the first latched ANDed signal and the multiple-bit count signal to provide a wait state control signal for initiating an insertion of one or more wait states on the signal bus.