Resource allocation with parameter counter in multiple requester system

Abstract

A controller for a single port (typically FIFO) memory for a computer system allocates the flow of data from a single port dynamic RAM to several data requesters such as a graphics engine, a CPU, and a display screen. One parameter is assigned to the display screen and a second parameter is assigned to the other data requester. Then each memory cycle is assigned in duty cycle fashion to the data requesters associated with one or the other of the parameters. Thus, typically the screen display which requires large amounts of data will have a relatively large parameter value associated with it such as six, while the single parameter value associated with the graphic engine and CPU will have a lower value such as two. The screen display will in response access the memory for six memory cycles consecutively, while the graphics engine and CPU will access the memory for only two memory cycles. The FIFO associated with the screen display is thus kept relatively full so that the screen is refreshed at all times and no FIFO empty detection is thus needed. The memory controller includes a loadable counter for counting down the loaded parameter, and a state machine for loading in the values, decrementing the values held in the counter, and switching between the two parameters.