Cache-based computer system employing a snoop control circuit with

Abstract

A cache-based computer system is provided with a snoop control circuit that implements a write-back suppression technique. The snoop control circuit controls the write-back and invalidation of dirty data within a cache memory during a DMA write operation to maintain the integrity of data within the computer system. If an alternate bus master initiates a burst transfer cycle that does not encompass an entire line of valid data, the alternate bus master asserts a snoop write-back signal that causes the snoop control circuit to effectuate the write-back to system memory of a corresponding dirty line in the cache memory. Integrity of the data within the system is thereby maintained. On the other hand, if the alternate bus master initiates a burst transfer cycle that does encompass an entire line of valid data, the altemate bus master deasserts the snoop write-back signal. When the snoop write-back signal is deasserted, the snoop control circuit advantageously suppresses the write-back of the corresponding dirty data in the cache memory, thereby attaining reduced traffic on the system bus. Since the DMA operation involved the transfer of an entire line of valid data, the integrity of data is maintained even though the write-back of the dirty line was suppressed. As a result, the bandwidth of the computer system may be improved and the overall performance of the system may be enhanced.