The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 1997

Filed:

Sep. 30, 1992
Applicant:
Inventors:

Keiko Yuki, Kawasaki, JP;

Yoso Igi, Kawasaki, JP;

Fumiaki Tahira, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395427 ; 395250 ; 395280 ; 395287 ; 395308 ; 395405 ;
Abstract

A memory access control system which performs a DMA transfer and allows a central control unit to perform a specific, required software operation. A central control unit sets a flag after running the specific software operation. The DMA transfer includes a first phase and a second phase, the first phase being a first transfer between a main memory and a first buffer memory and then a successive, second transfer between the main memory and a second buffer memory. The second phase is a transfer between a respective buffer memory and an external memory. A first DMA controller requests the first phase and controls the transfer of the second phase from a respective buffer memory when a transfer of the first phase from the main memory to the respective buffer memory ends, and prohibits a request for the first phase when the first transfer ends during a transfer of the second phase from the second buffer memory. A DMA request controller controls the request for the first phase and prohibits a request when the second transfer of the first phase ends and cancels the prohibition of a request when the flag of the central control unit is set. In response to a request for the first phase, an external bus control unit halts the operation of the central control unit and performs the first and second transfers of the first phase.


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