The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 1997

Filed:

Dec. 28, 1995
Applicant:
Inventors:

Mark H Babcock, Austin, TX (US);

James A Lamb, Coral Springs, FL (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
375316 ; 375340 ; 34082579 ;
Abstract

A logic circuit (260) includes recursive elements (470, 1070, 1400, 1600) interconnected in a matrix (300), and M data inputs (490), and a logic circuit output (475). In one embodiment, N+1 binary column setup inputs (485), and M-N binary row setup inputs (480) are also included. The matrix (300) is an arrangement of the recursive elements (470) in rows, columns, and diagonals. The M data inputs (490) are for coupling the M bits of the binary word to the recursive elements (470). The logic circuit output (475) includes an output (810) of one of the recursive elements (470, 1070, 1400, 1600). The logic circuit output (475) has a binary value determined by a comparison of the number of bits having a first binary value within the binary word, to the predetermined number, N. In the one embodiment, the comparison is determined by the values of the setup inputs (480), (485).


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