The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 1997
Filed:
Nov. 09, 1995
John V Gates, II, New Providence, NJ (US);
Gerard E Henein, Chatham, NJ (US);
Joseph Shmulovich, Murray Hill, NJ (US);
Lucent Technologies Inc., Murray Hill, NJ (US);
Abstract
Thermal expansion mismatch between solder and substrate can result in substrate cracking, especially in the case of brittle substrates, e.g., Si or glass. This problem can be substantially eliminated through use of a novel bonding pad structure that comprises a sacrificial layer and a confinement layer disposed on the former, with a window through the latter. The confinement layer (e.g., Ti or Cr) is selected to be substantially inert with respect to the solder (e.g, AuSn) at the soldering temperature, and the sacrificial layer (e.g., Au) is selected to interact with the solder at that temperature, such that the molten solder consumes at least some of the sacrificial material, with the interface between the molten material moving laterally underneath the confinement layer. After re-solidification of the molten material the structure effectively has a distributed interface between the resolidified material and the substrate, with attendant decrease of stress in the substrate. The novel approach has wide applicability, e.g., for soldering Si chips to a Si chip carrier, or for soldering an optical fiber to a Si/SiO.sub.2 substrate.