The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 15, 1997

Filed:

Jan. 20, 1995
Applicant:
Inventor:

Masato Nagamatsu, Ooita, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395379 ; 395382 ; 395392 ;
Abstract

In an instruction distribution control device for parallel execution of instructions for use in a superscalar parallel processor, the control device comprises an instruction distribution starting position pointer register, an instruction distribution enable/disable signal generating circuit, and an updating circuit. The distribution starting position pointer register indicates from which instruction of N (>1) instructions the distribution is to be started. The instruction distribution enable/disable signal generating circuit generates signals for determining whether the instructions may or may not be distributed to instruction executing arithmetic units on the basis of the contents of the instruction distribution starting position pointer register and signals indicating the results of dependence analysis for examining resource conflict. The updating circuit generates information indicating to which instruction of the N instructions the execution has advanced on the basis of the instruction distribution enable/disable signals and signals indicating the results of dependence analysis for examining data conflict and updates the instruction distribution starting position indicated by the instruction distribution starting position pointer register.


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