The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 15, 1997

Filed:

May. 22, 1995
Applicant:
Inventors:

Dong-Il Seo, Suwon, KR;

Se-Jin Jeong, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365 63 ; 365 51 ; 36523003 ;
Abstract

The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device and a method for arranging a signal line therein which can realize a high bandwidth by embodying a chip architecture being comprised of a multi I/O line. A semiconductor memory device includes arrays comprised of a plurality of reference blocks for storing a plurality of memory cells, a plurality of word lines extending in the direction of length of a chip, a plurality of bit lines extending in a vertical direction of length of a chip, each pair of bit lines being comprised of a bit line and a complementary bit line, a plurality of data I/O lines arranged on the upper portion of the arrays and extending in the vertical direction, each pair of data I/O lines being comprised of a data I/O line and a complementary data I/O line and being one by one connected to each pair of bit lines, and a plurality of column selection lines arranged in the vertical direction and adjacent to the data I/O line and complementary data I/O line, for controlling connection of each pair of bit lines to the data I/O lines.


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