Chopped hall sensor with synchronously chopped sample-and-hold circuit

Abstract

A chopped Hall sensor includes a Hall-element switching circuit of the kind in which a Hall element has two pairs of diagonally opposite Hall contacts which are alternately connected to a pair of DC supply conductors and to a pair of Hall-stitching-circuit output conductors for alternately, during phase .phi.1 and n.phi.1 of a first clock signal, switching the Hall exciting current from flow in one to another direction through the Hall element. A linear analog double-differential Hall-voltage amplifier has an input connected to the output of the Hall switching-circuit. A sample-and-hold circuit is comprised of first and second elemental sample-and-hold circuits (ESHCs) with inputs connected respectively to the two Hall-voltage differential-amplifier outputs. The first and second ESHCs are respectively clocked, by second and third clock signals, to the sample Hall voltage signal only during phases .phi.2 and .phi.3 and to hold the sample signal during phases n.phi.2 and n.phi.3 respectively, where .phi.2 and .phi.3 occur respectively during a mid portion of phases .phi.1 and n.phi.1. Two inputs of a summer circuit are connected respectively to the outputs of the first and second ESHCs. A third and fourth ESHC may be added to form a crossed-polarity full-differential sample-and-hold circuit. The Hall voltage amplifier may include a clocked noise blanking circuit for reducing the differential-gain of the amplifier only during a time span encompassing each phase transition in the first clock signal.