High speed semiconductor memory including a cache-prefetch prediction

Abstract

The high speed semiconductor memory includes at least one memory module and a cache controller. The at least one memory module includes a plurality of memory cells for storing data and a cache memory for storing part of the data stored in the plurality of memory cells, The cache controller includes a hit ratio counter for obtaining an average cache hit ratio and a comparator storing a desired threshold hit value and comparing the average cache hit ratio with the desired threshold value. The cache controller determines whether data corresponding to an input address are stored in the cache memory and allows to readout such data from the cache memory, otherwise controlling the read-out of data from the plurality of memory cells for storage in the cache memory so as to update the contents of the cache memory. A request signal for transferring data from the memory cells to the cache memory is generated when the average cache hit ratio is lower than the desired threshold value. The high speed memory further includes a prediction controller for selecting data to be transferred from the memory cells to the cache memory.