Analog-to-digital converter with optional low-power mode

Abstract

An IC chip having an analog-to-digital converter together with control circuitry for effecting switchover between normal-power mode and low-power mode. The control circuitry includes a first D-type flip-flop with reset which receives on its 'D' input a continuous high signal; on its differential clock inputs the flip-flop receives complementary logic signals derived from the 'conversion start' (CONVST) signal applied to one pin of an 8-pin chip. In normal mode, the CONVST signal is a short pulse having an initial negative-going (falling) leading edge, and the flip-flop responds to that leading edge by producing a high Q output (CONVEN). This signals the A/D converter to carry out a conversion. In low-power mode, the CONVST short pulse is positive. The subsequent negative-going (falling) trailing edge of the pulse activates the flip-flop to cause its Q output to go high and turn on the A/D converter. The control circuitry includes a second D-type flip-flop (this one with set) which receives on its D input the CONVST signal. The Q output. of the second flip-flop generates a mode switchover control signal (designated SLEEPB). During low-power mode, established by the use of positive-going CONVST pulses, the low CONVEN signal at the end of conversion clocks the second flip-flop to sample CONVST on its D input, thereby causing the Q output of the second flip-flop (SLEEPB) to go low and switch the A/D converter into low-power status.