The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 1997
Filed:
Aug. 31, 1994
Stephen M Curry, Dallas, TX (US);
Michael L Bolan, Dallas, TX (US);
Kevin E Deierling, Dallas, TX (US);
William L Payne, II, Garland, TX (US);
Hal Kurkowski, Dallas, TX (US);
Donald R Dias, Carrollton, TX (US);
Gary V Zanders, Dallas, TX (US);
Robert D Lee, Denton, TX (US);
Guenther H Lehmann, The Colony, TX (US);
Dallas Semiconductor Corporation, Dallas, TX (US);
Abstract
A serial-port memory is positioned in a substantially token-shaped body. The substantially token-shaped body has a perimeter and a flange extending from a portion of the perimeter. The serial-port memory comprises a serial port, a scratchpad memory coupled to the serial port, a second memory coupled to the scratchpad memory; and control logic coupled to the serial port and the scratchpad and second memories. The control logic transfers information from the scratchpad memory to the second memory as a block pursuant to a block transfer command received at the serial port. The electronic token has a first electrically conductive surface and a second electrically conductive surface that combines to create a hollow cavity and the serial port, scratchpad memory, second memory, and control logic positioned inside the hollow cavity, the first conductive surface and the second conductive surface can be electrically coupled to transmit electrical signals generated by the serial port, scratchpad memory, second memory, and control logic and to receive externally generated electrical signals. The first electrically conductive surface and the second electrically conductive surface are preferably planar. The control logic includes a cyclic redundancy check generator. Third and fourth memories can be coupled to the scratchpad memory, wherein the control logic transfers information as a block from the scratchpad memory to one of the second, third, and fourth memories pursuant to a block transfer command received at the serial port.