The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 1997

Filed:

Sep. 06, 1995
Applicant:
Inventor:

Cheol-seong Hwang, Seongnam, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438-3 ; 438396 ; 438253 ; 438240 ;
Abstract

A capacitor of a semiconductor device employing a material having a high dielectric constant or ferroelectric properties and a method for manufacturing the same are provided. The capacitor includes a plug film formed on a semiconductor substrate where a transistor having a gate electrode, a source region and a drain region is formed. An insulation film having a contact hole is formed on the plug film and a first diffusion-blocking film is formed on the plug film in the contact hole. A second diffusion-blocking film is then formed on the surface of the first diffusion-blocking film, the surface of the insulating film and on the sidewalls of the contact hole. A third diffusion-blocking film is formed on the second diffusion-blocking film and a first conductive layer is formed on the third diffusion-blocking film so as to be used for a storage electrode. A dielectric layer is formed on the first conductive layer, and a second conductive layer is formed on the dielectric layer to be used as a plate electrode. An iridium film or a ruthenium film is employed as a diffusion-blocking film that has a high conductivity and prevents silicon diffusion, to thereby obtain a larger electrostatic capacity in a small effective area and enable higher integration of a semiconductor memory device and enhance product reliability.


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