Direct-conversion receiver for digital-modulation signal with signal

Abstract

A direct-conversion receiver includes a direct-conversion demodulator. A first device detects a strength of a received signal. A clock signal generator outputs a clock signal in response to a reception start signal. The clock signal has a frequency corresponding to a symbol rate or higher. A second device samples an output signal of the demodulator at a timing determined by the clock signal. A third device samples an output signal of the first device at a timing determined by the clock signal. A fourth device stores 'n' output signals of the second device which relate to a signal periodically transmitted from a transmitting station 'n' times, wherein 'n' denotes a natural number equal to 2 or greater. A fifth device stores 'n' output signals of the third device which correspond in timing to the 'n' output signals of the second device. A sixth device reads out signals from the fourth device, and reads out signals from the fifth device. The sixth device weights the signals read out from the fourth device in response to the signals read out from the fifth device. A seventh device combines output signals of the sixth device.