The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 1997
Filed:
Feb. 21, 1995
Bernd K Koenemann, Hopewell Junction, NY (US);
William H McAnney, LaGrangeville, NY (US);
Mark L Shulman, Staatsburg, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In a level sensitive scan design (LSSD) circuit embodiment for testing the behavior of logic circuits, a mechanism is provided for generating a skewed load of data into a set of shift register scan string latches. The nature of the input scan string assures that a certain number of 0 to 1 or 1 to 0 transitions occurs as an input to the block of logic being tested. Furthermore, a mechanism for delaying by one system clock cycle time the capture of information from the logic block in a second shift register scan string provides a mechanism for testing for the occurrence of short paths and long paths while preserving testability for stuck-at faults. Furthermore, all of these advantages are achieved without impacting the traditional stuck-fault test capabilities of the level sensitive scan design methodology.