The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 1997
Filed:
Dec. 12, 1995
Jei-Hwan Yoo, Kyungki-do, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
A test control circuit and method for performing a standardized test in a semiconductor memory device which has a structure such that it is difficult to perform a test operation using a standardized test mode. The test control method of a semiconductor memory device includes the steps of: arranging in the memory device a fuse capable of being electrically blown; receiving a plurality of external input signals applied to the memory device; generating a blocking signal based on the plurality of external input signals and the status of the electrical fuse; generating a parallel test enable signal based on the blocking signal and the plurality of external input signals, wherein, when the blocking signal is of a first logic level, the parallel test enable signal will indicate performance under either a parallel test mode or a normal operation mode based on the plurality of external input signals, and when the blocking signal is of a second logic level, the fuse is blown and the parallel test enable signal permanently indicates operation in a normal opreration mode.