Cache memory system and method thereof for storing a staged memory item

Abstract

An embodiment of the present invention is a cache memory system for providing memory items staged from an, external memory to a logic unit. The system consists of a cache array comprising at least one single cache array structure wherein one such single cache array structure consists of a plurality of cache entries. Each of the cache entries consists of a memory item section for storing at least a portion of a memory item and a cache tag section for storing at least a portion of a cache tag. Each such cache tag identifies at least one of the cache entries. The cache array is responsive to address signals for reading out the contents of at least one of the cache entries. The system further consists of a logic circuit responsive to memory requests for generating the address signals and consists of a circuit for comparing the cache tags to the memory requests for a predetermined relationship. The system further consists of an address bus interconnecting the cache array and the logic circuit for carrying the address signals to the cache array and a data bus interconnecting the cache array and the logic circuit for carrying the cache tags and the memory items between the cache array and the logic circuit.