The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 1997
Filed:
Jan. 30, 1996
David B Rees, Basingstoke, GB;
Martin J Steadman, London, GB;
Cypress Semiconductor, Inc., San Jose, CA (US);
Abstract
A bi-directional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2, involves controlling the voltage V1 on gate of MN1 using a gate node N1 that is coupled to supply voltage VCC under the control of two transistor pairs MN3, MN4 and MP3, MP4 that sense the voltages on IO1 and IO2, and an inverter pair MP2, MN2 having a voltage signal ENB input on its gates. If the voltages on nodes IO1 and IO2 both go high, MP3 and MP4 tend to turn OFF dropping gate voltage V1, via MP2, below VCC and tending to turn MN1 OFF. Leakage from node N1 in such event occurs through a small current bleed network formed by three transistors MN6, MN7, and MN8.