The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 1997

Filed:

Aug. 11, 1993
Applicant:
Inventor:

Katsushi Asahina, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
327 89 ; 327 97 ; 327328 ; 327374 ; 327333 ; 326 17 ; 326 68 ;
Abstract

There is disclosed an input circuit for a semiconductor integrated circuit device wherein a level shift circuit (LS1) adds a constant voltage to an input signal from an input signal terminal (3) and a reference voltage from a reference voltage terminal (4) to output signals, which are in turn amplified by means of a plurality of cascaded, first and second differential amplifier circuits (Dif1, Dif2), and then a difference between the amplified input signal and the amplified reference voltage is applied to a CMOS inverter circuit (In1), which in turn outputs a power supply potential (V.sub.DD) or a ground potential (V.sub.SS) in accordance with the difference, thereby achieving a high-speed operation in response to the binary input signal slightly varying in signal voltage and a normal operation independent of variation of the reference voltage. (FIG. 1 )


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