Method and apparatus for buffering a user application from the timing

Abstract

A method and apparatus for data storage and retrieval including first and second banks of refreshable memory, such as DRAMs. The user application provides a write clock and a read clock, the read clock being independent of the write clock. FIFO buffers are provided between the user application and the memory, with the buffers providing for read data with associated addresses and write data with associated addresses. A DRAM controller system is provided including a timing generator for the DRAM controlled by an external clock. The controller system controls the buffers to enable the continuous writing of user data to one of the first and second banks at a given address, with the user address and data synchronized to the write clock, while enabling simultaneous reading of data at a user provided address from the other of the first and second banks, with the loading of read addresses and outputting of read data occurring continuously and synchronously to the read clock. Refresh of the memory occurs when the read or write buffer is not full.