The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 1997
Filed:
Jun. 05, 1995
Applicant:
Inventor:
Haruki Yahata, Tokyo, JP;
Assignee:
Kabushiki Kaisha Toshiba, Kanagawa-ken, JP;
Primary Examiner:
Int. Cl.
CPC ...
G04B / ; G04F / ; H04L / ;
U.S. Cl.
CPC ...
368 10 ; 368 46 ; 368156 ; 375356 ;
Abstract
A clock synchronizing apparatus is constructed of a multi-input PLL circuit. The multi-input PLL circuit comprises a phase comparator, a variable frequency oscillator, a loop filter, and an adding device. The phase comparator includes a plurality of subtracting devices for subtracting an output signal from each of input signals and a plurality of amplifiers for obtaining a phase comparison characteristic corresponding to the output signal of each subtracting device and for amplifying each phase comparison characteristic by a predetermined gain. Each gain is predetermined for each input signal. One dominant gain is greater than the sum of the other gains.