The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 1997

Filed:

May. 25, 1995
Applicant:
Inventor:

Hideo Matsui, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364757 ; 364754 ;
Abstract

A multiplying apparatus, capable of processing in relatively high speed with relatively small hardware quantity, in which the circuits for relative-digits are composed of adders 1a, 1b, 1c, 1d, first D-flip flops 3a, 3b, 3c, 3d propagating the respective digits of a multiplier while latching them successively in synchronism with the clock CLK, second D-flip flops 2a, 2b, 2c, 2d latching either the respective additional results of the adders of the digits of themselves or the respective additional results of the adders of the next digits according to respective values being latched by the first D-flip flops 3a, 3b, 3c, 3d in synchronism with the clock CLK, and delay circuits 5a, 5b, 5c delaying the propagation of the clock CLK to the next digit until the adders 1a, 1b, 1c, 1d for the respective digits output the respective carries, in other words, until the adders 1a, 1b, 1c, 1d finish the respective additional operations.


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