The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 1997
Filed:
Jun. 22, 1995
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A protection system for an integrated circuit includes a protection structure for the input terminals and output terminals that protects against ESD stress in bonding pad to V.sub.SS and bonding pad to V.sub.DD paths, both negative and positive paths. The protection system also includes a protection structure for protecting bonding pad to bonding pad electrical paths and a protection structure for V.sub.DD to V.sub.SS paths. Using all three protection structures in combination provides full protection against ESD events in all possible paths in an integrated circuit. A protection structure isolates an output buffer from the protection structure and encourages stress discharge through the protection structure rather than the output buffer. In addition, a set of design rules is set forth for the design and layout of the output buffer and protection structure including rules pertaining to transistor width, finger width, channel length, contact to gate spacing, and the like which significantly enhance ESD protection. In one embodiment, an electrostatic discharge (ESD) protection circuit connected to a pad of a semiconductor integrated circuit includes an NMOS transistor having a gate and a source/drain pathway connected between the pad and ground, a resistor connected between the NMOS transistor gate and ground, and a clamping transistor having a source/drain pathway connected between the NMOS transistor gate and ground and having a gate connected to the NMOS transistor gate. Supply taps are positioned at a distance removed from the NMOS transistor so that the substrate resistance at the NMOS transistor is elevated.