Voltage-controlled oscillator circuit

Abstract

There is disclosed a voltage-controlled oscillator circuit capable of being operated at low power supply voltages and accomplishing low electric power consumption. The circuit permits the duty cycle to be controlled well. The circuit is capable of operating at high speeds. The circuit comprises a first and a second dynamic latch circuits producing oscillation output. Each dynamic latch circuit consists of a series combination of a P-channel MOS transistor and an N-channel MOS transistor. An output terminal is connected to the junction of these two transistors. The output from each latch circuit is inverted according to the voltage at the gate of each MOS transistor and dynamically latches the state of the output. This inversion is performed by turning on the MOS transistors by first and second capacitive elements and by first and second comparator circuits. The capacitive elements are charged and discharged by the outputs from the dynamic latch circuits. Voltages for charging the capacitive elements are applied to the comparator circuits. The switching operation is performed at a higher speed than where a flop-flop is used. Consequently, the oscillation frequency is improved. These MOS transistors do not simultaneously conduct and so electric currents passing through the transistors can be suppressed. Since the timing at which the inversion is made is determined by the charging rates of the capacitive elements, the duty cycle can be controlled well.