High-accuracy, low-power peak-to-peak voltage detector

Abstract

An accurate peak-to-peak detector, readily implemented in CMOS and consuming low power. The peak-to-peak detector includes a clamp portion (circuit) followed by a peak-detect portion (circuit), each of which circuits includes at least one active component (e.g., transistor). The clamp circuit receives an input signal having an alternating current (AC) component via an input coupling capacitor which outputs a voltage on a line to the peak-detect circuit. The clamp circuit includes either a passive load element (e.g., a resistor), or an active load element (e.g., a CMOS transistor), so that the clamp circuit bleeds current from the input coupling capacitor, and any slow drift in the DC level of the input voltage will be followed. The peak-detect circuit follows the voltage output by the coupling capacitor, and includes either a passive load element (e.g., a resistor) or an active load element (e.g., a CMOS transistor), to bleed current from the peak-detected signal so that decreases in peak-to-peak amplitude of the input voltage will be followed. Various CMOS embodiments are described which use only N-Channel transistors, only P-Channel transistors, or both N-Channel and P-Channel transistors.