The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 1997

Filed:

Jan. 02, 1996
Applicant:
Inventors:

Makoto Shichi, Kariya, JP;

Mamabu Hayakawa, Kariya, JP;

Dennis M Wright, Eastlake, OH (US);

Assignee:

Allen-Bradley Company, Inc., Milwaukee, WI (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01H / ;
U.S. Cl.
CPC ...
307130 ; 307125 ; 307139 ; 307141 ; 327143 ; 327261 ; 327381 ; 363 74 ; 323234 ;
Abstract

The present invention provides a switching device incorporating a simple circuit capable of avoiding the flash-on of a transistor when a power supply is turned on and off thereby reducing the OFF delay time. The output circuit comprises a FET (145) having a drain and a source connected in series to a current line for supplying a current from a power supply (VD) to an output detector (load) (L), and a photocoupler (149) for applying a driving voltage across the gate and the source of the FET (145) according to the output of an internal circuit (151), a differentiation circuit comprising a capacitor (7) and resistors (5,9) is connected across the drain and the source of the FET (145), and second transistor (3) having a collector and an emitter connected to the gate and the soruce of the FET (145) is driven by a charging current for charging the capacitor (7). When a voltage applied across the drain and the source of the FET (145) starts rising, the second transistor (3) is turned on to turn off the FET (145) forcibly.


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