Multilevel gate array integrated circuit structure with perpendicular

Abstract

A multilevel gate array MOS-type integrated circuit structure is described wherein each source, drain, and gate electrode region in the integrated circuit structure is accessible directly through a contact opening formed normal to the plane of the underlying substrate through an overlying insulation layer. The multilevel gate array MOS-type integrated circuit structure of the invention comprises a substrate; a first semiconductor device level comprising one or more first source regions, one or more first drain regions, and one or more first gate electrode regions; and a second semiconductor device level formed over the first semiconductor device level and comprising one or more second source regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying first source region in the first level, one or more second drain regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying drain region in the first level, and one or more second gate electrode regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying gate electrode region in the first level; whereby contact openings may be formed, normal to the plane of the substrate, to each of the source, drain, and gate electrode regions in both semiconductor device levels.