The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 1997

Filed:

Oct. 27, 1995
Applicant:
Inventor:

Jong-Hyon Ahn, Suwon, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 62 ; 437152 ; 437984 ;
Abstract

A method for manufacturing a semiconductor substrate structure wherein a comprising the steps of defining bulk transistor and SOI transistor areas, the bulk transistor area disposed on a lower single crystalline silicon layer, and the SOI transistor area diposed on an upper single crystalline silicon layer. The method characterized in that a spacer is formed on a portion of the bulk transistor area which covers a sidewall of the SOI transistor area, a first conductive well is formed in the lower single crystalline silicon layer and a well oxide layer is formed over the first conductive well region, a second conductive well is formed in the lower single crystalline silicon layer between the SOI transistor layer and the first conductive well, and the first conductive well is rediffused.


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