The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 1997
Filed:
Mar. 27, 1995
Mark R Schneider, San Jose, CA (US);
Robert T Trabucco, Los Altos, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A planar substrate is attached to a face of a semiconductor die. The semiconductor die is electrically connected to a printed wiring board and encapsulation material covers the peripheral edges of the planar substrate, semiconductor die, and means for interconnecting the die and printed wiring board. An exterior face of the planar substrate remains exposed and may be utilized in pick and place automatic assembly. The exterior face of the planar substrate may also be utilized for attachment of an external heat sink for improved heat transfer from the semiconductor device. The planar substrate may be comprised of silicon, ceramic, metal or any other stiff material so long as the temperature coefficient of expansion is similar to that of the semiconductor die. A flip-chip semiconductor die may also be utilized without a planar substrate wherein the nonactive face of the die is exposed.