The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 1997

Filed:

Dec. 28, 1993
Applicant:
Inventor:

Eui Y Oh, Kyungki-do, KR;

Assignee:

LG Electronics Inc., Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 21 ; 437 40 ; 437 42 ; 437978 ; 148D / ; 430319 ;
Abstract

A method for fabricating a thin film transistor, enabling an easy fabrication and an improvement in device characteristic by use of a self-alignment. The method including the steps of forming a gate electrode on an insulating transparent substrate, depositing a plurality of gate insulating films having different refractive indexes, in the order of higher refractive index, and then a semiconductor layer, an etch stopper layer and a photoresist film, in this order, subjecting the resulting structure to a back light exposure using the gate electrode as a mask and then to a development for patterning the photoresist film so that the gate electrode can be overlapped by a predetermined overlap length with each of a source electrode and a drain electrode to be formed at a subsequent step, selectively etching the etch stopper layer using the patterned photoresist film as a mask, removing the patterned photoresist film and then sequentially depositing a high concentration n type doped semiconductor layer and a metal layer over the entire exposed surface of the resulting structure, and selectively removing respective portions of the high concentration n type doped semiconductor layer and the metal layer disposed over the patterned etch stopper layer to form the source electrode and the drain electrode.


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