The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 1997
Filed:
May. 19, 1995
Farzad Khosrowpour, Austin, TX (US);
Dell USA L.P., Austin, TX (US);
Abstract
A fault tolerant isolation system providing fault tolerant electrical isolation between different components receiving power from separate power sources regardless of which of the power sources fails. One power source provides operating voltage to an isolation device, which is a transceiver, buffer, quick switch, etc. The other power source activates a transistor switch coupled to the output enable input of the isolation device, and a current limit device is provided between the output enable and power inputs of the isolation device. In this manner, failure of either power source disables the isolation device and therefore provides fault tolerant isolation between the devices on either side. In the preferred embodiment, the isolation device acts as a high impedance open switch if its power is removed thereby isolating the devices on either side. The transistor switch is implemented using a field-effect transistor (FET), which is deactivated when the other source fails, where the output enable is pulled high by the first power source thereby disabling the outputs of the isolation device. Voltage drop devices such as diodes may be used to lower the voltage of either source to the appropriate operating voltage of the isolation device, if necessary.