The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 1997

Filed:

May. 19, 1995
Applicant:
Inventors:

Son H Ho, Sunnyvale, CA (US);

Hien Nguyen, San Jose, CA (US);

Assignee:

Cirrus Logic Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
371 221 ; 371 251 ; 371 671 ; 326 16 ; 327199 ;
Abstract

A test logic circuit for testing the functioning of an integrated circuit containing asynchronous logic and synchronous logic and state machines is provided with a comparison circuit that compares state numbers produced by one of the state machines to a defined target value. The comparison circuit asserts a signal when one of the state numbers is equal to the defined target value. Status latches are coupled to the comparison circuit and latch a status of the asynchronous logic in response to the assertion of the signal by the comparison circuit. The comparing of the state numbers to a defined target value by the comparison circuit in the test logic circuit allows the latching of the status of the asynchronous logic upon the state machine reaching the specified state, and thereby provides the speed necessary to determine the status of the asynchronous logic for a particular state of a state machine in the integrated circuit.


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