High speed rom decode circuit

Abstract

A decode circuit which permits large address decoding (corresponding to an increase in the number of ROM words) and/or an increase in the number of bits per word line while preserving ROM speed. This is accomplished by providing a positive feedback arrangement at the decode circuit output to speed up the increase in voltage at the decode circuit output during the pulldown phase of the clock cycle. As the voltage at an output line of the decode circuit is increasing through a first p-channel transistor coupled to a voltage supply, a second n-channel transistor having its gate coupled to the decode circuit output line is turned on and thereby applies a ground potential to the gate of the first transistor. This ground potential causes the first transistor to conduct even more rapidly and thereby increase the voltage at the decode circuit output more rapidly. This, in turn, causes the second transistor to apply ground potential to the gate of the first transistor even more rapidly. The result is that the output of the decode circuit is raised to approximately the supply voltage during the pulldown portion of the clock cycle much more rapidly than in prior art decode circuits that do not use the positive feedback arrangement of the present invention. The result is that prior art circuits can be made to operate with greater speed or can be provided with additional word lines and/or bit lines without decrease in speed.