The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 1997

Filed:

Jul. 21, 1995
Applicant:
Inventors:

Hefeng Wang, Tokyo, JP;

Tetsuo Onodera, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03G / ;
U.S. Cl.
CPC ...
330134 ; 330138 ; 330279 ; 330280 ; 455126 ;
Abstract

A power control circuit having a saturation preventing control loop including a variable gain amplifier, an RF power amplifier, a directional coupler, a detecting circuit, a comparator, a switch, and an adder. When the signal level of an output signal of the comparator is low, the switch is turned on. When the signal level of the output signal of the comparator is high, the switch is turned off. A system power control loop includes a system power control terminal, the adder, and the variable gain amplifier. Since the saturation preventing control loop is provided with the switch, the saturation preventing control loop operates only when the signal level of the amplified signal is larger than a reference value. The system power control loop can properly operate according to a system power control signal supplied from the system power control terminal.


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