The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 1997
Filed:
May. 05, 1995
Andrew T Appel, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of forming a CMOS transistor which comprises providing a partially fabricated CMOS structure having a p-type region wherein NMOS devices will be fabricated and an n-type region wherein PMOS devices will be fabricated, a separate pattern defining each region, a thin gate oxide layer in each window and a thin polysilicon gate layer having a thickness up to 3200 .ANG. over the thin gate oxide layer having a thickness up to 90 .ANG.. A layer of glass having a boron doping species therein, preferably borosilicate glass, is deposited over the polysilicon gate layer disposed over the the n-type region. The portion of the polysilicon gate layer disposed defining the p-type region is then doped n-type, preferably by implanting phosphorus, and the structure is heated to cause boron to diffuse from the layer of glass into the polysilicon gate layer over the n-type region. The layer of glass of glass is removed and fabrication of the CMOS device is then completed in standard manner.