Static random access memory sense amplifier

Abstract

A memory sense amplifier for a static random access memory includes a pair of transistor amplifiers respective to the bit lines threading the memory. The power consumed is minimized without sacrificing speed of operation by temporarily connecting the source electrodes of the transistor amplifiers to the bit lines to allow them to track the states of the bit lines before a current path is completed to the drains of the transistors to allow them to draw current from the bit lines, thereby minimizing the time that the sense amplifiers are permitted to draw current from the bit lines. In addition, an economy of circuitry is achieved by eliminating the need for a separate latch circuit by disconnecting the sense amplifiers from the bit lines and thereafter enabling them to latch the information state read from the bit lines. The memory cycle is defined in four distinct phases ('PRECHARGE', 'SENSE', 'SELECT', and 'HOLD'), instead of in two phases ('clock' and 'select') followed by indeterminate length self-timed intervals as provided in prior art U.S. Pat. No. 5,309,395.