The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 1997
Filed:
Jan. 29, 1996
Richard A Erhart, Chandler, AZ (US);
Thomas W Ciccone, Paradise Valley, AZ (US);
Vivid Semiconductor, Inc., Chandler, AZ (US);
Abstract
CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by providing each input signal as dual input signals that track each other within two different voltage ranges. A shield voltage is provided approximately midway between the uppermost and lowermost power supply voltages. The first input signal ranges between the lowermost power supply voltage and the shield voltage, and the second input signal ranges between the shield voltage and the uppermost power supply voltage. The first and second input signals drive the gates of n-channel and p-channel CMOS switching transistors, respectively, the drain terminals of which are coupled to first and second output terminals, respectively. N-channel and p-channel shield transistors are connected in series between the first and second output terminals, and have their gate terminals coupled to the shield voltage.