Semiconductor integrated circuit device

Abstract

The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the same, in which at least one of the circuits includes a totem-pole output stage of a first NPN bipolar transistor, on the power supply terminal side, and a second NPN bipolar transistor, on the ground side; a first differentiator circuit for providing pulsing action to the base of the first NPN transistor; a pair of series-connected PMOS transistors for controllably driving the second NPN transistor; and feedback MOS transistors for quickening turn-off of the output stage transistors. The circuit can be effected with a second differentiator circuit in place of the series-connected pair of PMOS transistors. Arrangements of circuits can also be effected in which the totem-pole connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side. With such circuit configurations, the output signal swing is maximized, and the differentiator circuit provides for temporary saturation along with a quickened recovery therefrom, thereby reducing transmission delay time and achieving low power consumption. The device can be implemented by circuitry which employs the bootstrap effect as well as IIL (I.sup.2 L) design schemes.