The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 1997
Filed:
Feb. 08, 1995
Narasimhareddy L Annapareddy, San Jose, CA (US);
Damon W Finney, San Jose, CA (US);
Michael O Jenkins, San Jose, CA (US);
Larry B Kessler, San Jose, CA (US);
Donald J Lang, Cupertino, CA (US);
Song C Liang, San Jose, CA (US);
David N Mora, San Jose, CA (US);
David A Plomgren, San Carlos, CA (US);
Peter P Urbisci, San Jose, CA (US);
Andrew D Walls, San Jose, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An interconnection network comprises a pair of backplanes for receiving X pluggable node cards. The pair of backplanes include X backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group includes X/2 connectors. A first backplane includes first permanent wiring which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane includes second permanent wiring which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets' of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection. Each node card includes a processor and a switch module which simultaneously connects the processor to at least plural connectors of a backplane connector group.