The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 1997
Filed:
May. 15, 1995
Jerzy Wieczorkiewicz, Kanata, CA;
Krishna Shetty, Kanata, CA;
Terry Kenny, Nepean, CA;
Robert L van der Valk, Rotterdam, NL;
Menno T Spijker, Rotterdam, NL;
Mitel Corporation, Kanata, CA;
Abstract
A digital phase locked loop for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop included a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in the output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator.