Pipeline-operating type memory system capable of reading data from a

Abstract

A pipeline-operating type memory system is arranged to have a first input unit for receiving a selector address signal for selecting data, a second input unit for receiving at least an address strobe signal, an X address signal and a Y address signal for selecting data; a first unit for receiving the X address signal and the Y address signal, latching these signals utilizing a first clock signal, and continuously outputting at least either of the X and the Y address signals until these address signals are unlatched; and a second unit for latching a selector address data signal output from the first input unit utilizing the first clock signal, and continuously and selectively outputting at least either of the address signal until the signal is unlatched. The memory system operates to transfer data in a manner to suit the pipeline operating cycle at a normal operating mode and at a fast page mode.